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DS1217A
DS1217A Nonvolatile Read/Write Cartridge
FEATURES
PIN ASSIGNMENT
Name Ground +5 Volts Write Enable Address 13 Address 8 Address 9 Address 11 Output Enable Address 10 Cartridge Enable Data I/O 7 Data I/O 6 Data I/O 5 Data I/O 4 Data I/O 3 Position A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 Name No Connect Address 14 Address 12 Address 7 Address 6 Address 5 Address 4 Address 3 Address 2 Address 1 Address 0 Data I/O 0 Data I/O 1 Data I/O 2 Ground
* User-insertable * Capacity up to 32K x 8 * Standard
bytewide pinout facilitates connection to JEDEC 28-pin DIP socket via ribbon cable
* Data retention greater than 10 years * Automatic
write protection circuitry safeguards against data loss
* Manual switch unconditionally protects data * Compact size and shape * Rugged and durable * Wide operating temperature range of 0C to 70C
OFF - ON
3"
A1 B1
See Mech. Drawings Section
DESCRIPTION
The DS1217A is a nonvolatile RAM designed for portable applications requiring a rugged and durable package. The nonvolatile cartridge is available in densities ranging from 2K x 8 to 32K x 8 in 8K byte increments. A card edge connector is required for connection to a host system. A standard 30-pin connector can be used for direct mount to a printed circuit board. Alternatively, remote mounting can be accomplished with a 28-conductor ribbon cable terminated with a 28-pin DIP plug. The remote method can be used to retrofit existing systems that have JEDEC 28-pin bytewide memory sites. The DS1217A cartridge has a lifetime energy source to retain data and circuitry needed to automatically protect memory contents. Reading and writing the memory locations is the same as using conventional static RAM. If the user wants to convert from read/write memory to read-only memory, a manual switch is provided to unconditionally protect memory contents.
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DS1217A
READ MODE
The DS1217A executes a read cycle whenever WE (write enable) is inactive (high) and CE (cartridge enable) is active (low). The unique address specified by the 15 address inputs (A0-A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the eight data I/O pins within tACC (access time) after the last address input signal is stable, providing that CE and OE (output enable) access times are also satisfied. If OE and CE times are not satisfied , then data access must be measured from the latter occurring signal (CE or OE); the limiting parameter is either tCO for CE or tOE for OE rather than address access. Read cycles can only occur when VCC is greater than 4.5 volts. When VCC is less than 4.5 volts, the memory is inhibited and all accesses are ignored.
during power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects the external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.5 volts. The DS1217A checks battery status to warn of potential data loss. Each time that VCC power is restored to the cartridge, the battery voltage is checked with a precision comparator. If the battery supply is less than 2.0 volts, the second memory cycle is inhibited. Battery status can, therefore, be determined by performing a read cycle after power-up to any location in memory, recording that memory location content. A subsequent write cycle can then be executed to the same memory location, altering data. If the next read cycle fails to verify the written data, the contents of the memory are questionable. In many applications, data integrity is paramount. For this reason, the cartridge provides battery redundancy. The DS1217A features an internal isolation switch that provides for the connection of two batteries. During battery backup time, the battery with the highest voltage is selected for use. If one battery fails, the other will automatically take over. The switch between batteries is transparent to the user. A battery status warning will occur if both batteries are less than 2.0 volts.
WRITE MODE
The DS1217A is in the write mode whenever both the WE and CE signals are in the active (low) state after address inputs are stable. The last falling edge to occur of either CE or WE will determine the start of the write cycle. The write cycle is terminated by the first rising edge of either CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active) then WE will disable the outputs in tODW from its falling edge. Write cycles can only occur when VCC is greater than 4.5 volts. When VCC is less than 4.5 volts, the memory is write protected.
REMOTE CONNECTION VIA A RIBBON CABLE
Existing systems that contain 28-pin bytewide sockets can be retrofitted using a 28-pin DIP plug. The DIP plug, AMP Part Number 746616-2, can be inserted into the 28-pin site after the memory is removed. Connection to the cartridge is accomplished via a 28-pin ribbon cable connected to a 30-contact card edge connector, AMP Part Number 499188-4. The 28-pin ribbon cable must be right-justified such that positions A1 and B1 are left disconnected. For applications where the cartridge is installed or removed with power applied, both ground contacts (A1 and B15) on the card edge connector should be grounded to further enhance data integrity. Access time push-out may occur as the distance between the cartridge and driving circuitry is increased.
DATA RETENTION MODE
The Nonvolatile Cartridge provides full functional capability for VCC greater than 4.5 volts and guarantees write protection for VCC less than 4.5 volts. Data is maintained in the absence of VCC without any additional support circuitry. The DS1217A constantly monitors VCC. Should the supply voltage decay, the RAM is automatically write protected below 4.5 volts. As VCC falls below approximately 3.0 volts, the power switching circuit connects a lithium energy source to RAM. To retain data
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DS1217A
CARTRIDGE NUMBERING Table 1
PART NO. DS1217A/16K-25 DS1217A/64K-25 DS1217A/128K-25 DS1217A/192K-25 DS1217A/256K-25 DENSITY 2K x 8 8K x 8 16K x 8 24K x 8 32K x 8 UNUSED ADDRESS INPUTS *Address 11, 12, 13, 14 *Address 13, 14 *Address 14
*Unused address inputs must be held low (VIL).
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DS1217A
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Connection Relative to Ground Operating Temperature Storage Temperature -0.3V to +7.0V 0C to 70C -40C to +70C
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage SYMBOL VCC VIH VIL MIN 4.5 2.2 0.0 TYP 5.0 MAX 5.5 VCC +0.8 UNITS V V V
(0C to 70C)
NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current I/O Leakage Current CE VIH VCC Output Current @ 2.4V Output Current @ 0.4V Standby Current CE=2.2V Operating Current SYMBOL IIL IIO IOH IOL ICCS1 ICCO1 MIN -60 -10 -1.0 2.0 -2.0 3.0 5.0 35 TYP
(0C to 70C; VCC=5V 10%)
MAX. +60 +10 UNITS A A mA mA 10 75 mA mA NOTES
CAPACITANCE
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN TYP MAX. 75 75 UNITS pF pF
(tA = 25C)
NOTES
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DS1217A
AC ELECTRICAL CHARACTERISTICS
PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time from WE SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR tODW tOEW tDS tDH 5 100 20 5 250 170 0 20 5 MIN 250 TYP
(0C to 70C; VCC=5V 10%)
MAX UNITS ns 250 125 250 ns ns ns ns 125 ns ns ns ns ns ns 100 ns ns ns ns 5 5 4 4 3 5 5 NOTES
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DS1217A
READ CYCLE (1)
ADDRESSES VIH VIL tACC VIH CE VIH OE tCOE tCOE DOUT VIL VIL tOE tCO
tRC VIH VIL tOH VIH tOD VIH tOD VOH VOL OUTPUT DATA VALID VOH VOL VIH VIL
WRITE CYCLE 1 (2), (6), (7)
ADDRESSES VIH VIL tAW CE
tWC VIH VIL VIH VIL
VIL tWP
VIL tWR VIH VIL
HIGH IMPEDANCE
WE
VIH VIL tODW
tOEW
DOUT
tDS VIH DIN VIL DATA IN STABLE
tDH VIH VIL
WRITE CYCLE 2 (2), (8)
ADDRESSES VIH VIL tAW CE
tWC VIH VIL tWR tWP VIH VIL VIL VIL VIH VIH VIH VIL
WE tCOE DOUT
VIL tODW
VIL
tDS VIH DATA IN STABLE VIL
tDH VIH
DIN
VIL
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DS1217A
POWER-DOWN/POWER-UP CONDITION
VCC 4.50V
3.2V tF tPD tREC tR
CE
LEAKAGE CURRENT IL SUPPLIED FROM LITHIUM CELL
DATA RETENTION TIME tDR
POWER-DOWN/POWER-UP TIMING
SYM tPD tF tR tREC PARAMETER CE at VIH before Power-Down VCC Slew from 4.5V to 0V (CE at VIH) VCC Slew from 0V to 4.5V (CE at VIH) CE at VIH after Power-Up MIN 0 100 0 2 125 MAX UNITS s s s ms
(0C to 70C)
NOTES 10
10
(tA = 25C)
SYM tDR PARAMETER Expected Data Retention Time MIN 10 MAX UNITS years NOTES 9
WARNING:
Under no circumstances are negative undershoots, of any amplitude, allowed when the device is in battery backup mode.
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DS1217A
NOTES:
1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during the write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH, tDS are measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output buffers remain in a high impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition in Write Cycle 1, the output buffers remain in a high impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remains in a high impedance state during this period. 9. Each DS1217A is marked with a 4-digit date code AABB. AA designates the year of manufacture; BB designates the week of manufacture. The expected tDR is defined as starting at the date of manufacture. 10. Removing and installing the cartridge with power applied may disturb data.
DC TEST CONDITIONS
Outputs Open t Cycle = 250ns All Voltages Are Referenced to Ground
AC TEST CONDITIONS
Output Load: 100pF + 1TTL Gate Input Pulse Levels: 0 - 3.0V Timing Measurement Reference Levels Input: 1.5 V
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